Logic analyzers are digital data acquisition instruments that allow a user to acquire and analyze digital data from a large number of logic signals, such as all of the address, data and control signals associated with a microprocessor. Each logic signal is compared to a logic threshold or thresholds and results in one of two logic states; namely, high or low, one or zero, true or false. The behavior of groups of these signals can then be monitored to analyze the behavior of the circuitry or instrument under test.
U.S. Pat. No 5,526,286, issued Jun. 11, 1996, to Sauerwein et al. for “Oversampled Logic Analyzer” discloses a digital oversampling system and is incorporated herein by reference in its entirety. In the disclosed oversampled logic analyzer, all data and clock signal inputs are acquired asynchronously at high speed using a digital fast-in slow-out (FISO) acquisition circuit which produces a plurality of parallel high-speed data samples within each cycle of an internal system clock. The sample interval utilized is greater than the setup-and-hold time of the sampling device. In the disclosed oversampled logic analyzer, various mechanisms are described that ensure that, the resulting samples are monotonic and statistically independent.
Unfortunately, practical ratios of oversampling limit the resolution of edge detection to a resolution that is too coarse to support the small setup and hold windows required by synchronous buses whose clock rate is significantly faster than the logic clock of the oversampled logic analyzer. Moreover, the described oversampled logic analyzer cannot detect more than one clock edge and store more than one related data sample per channel for each logic clock. Because it rejects any clock edges that occur within one logic clock period of any previously detected edge, its maximum synchronous rate is asymptotically limited to be less than the logic clock rate used.
Some of the above deficiencies were addressed in U.S. Pat. No 5,854,996, issued Dec. 29, 1998 to Overhage et al. for “LOGIC SIGNAL EXTRACTION,” which patent application is incorporated herein by reference in its entirety. The Overhage arrangement addresses the edge resolution problem by storing the data as multi-bit analog samples and applying the Nyquist sampling theorem to interpolate the threshold crossing points of each signal to a much finer time resolution than the sample interval itself. Overhage discloses a method of precisely placing the data sample point relative to that edge by applying a mathematic time offset. In this manner, the logic clock limitation is avoided, since there is no real-time logic. That is, all the threshold comparison, edge detection and logic sampling is performed after the acquisition by processing the analog samples in a post processing manner via software.
Unfortunately, this approach is limited as a synchronous logic analyzer because: (1) the memory depths that can be practically implemented with analog sampling are several orders of magnitude smaller than logic analyzer implementations achieved and are effectively even shorter because many analog samples are necessary for each data clock period in order to achieve adequate edge placement accuracy; (2) using post-acquisition processing to derive state samples does not allow any inherent mechanism for the type of real-time complex logic triggering and storage qualification of the synchronous clocked data that logic analyzers provide; and (3) it is more difficult to achieve the channel densities required by logic state analyzer applications using analog sampling than it is using pure digital sampling.